1. Technical Field
Embodiments of the present disclosure are related to the field of integrated circuit, and in particular, to power supply clamp circuits for protection against electrostatic discharge events.
2. Description of Related Art
Electrostatic discharge (ESD) refers to the phenomenon of electrical discharge of high current for a short time duration resulting from a buildup of static charge on a particular integrated circuit (IC) package, or on a nearby human handling of that particular IC package. ESD events can have serious detrimental effects on manufacture and performance of ICs and other microelectronic devices, systems that contain such devices, and manufacturing facilities that produce them.
Power supply clamps for electrostatic discharge (ESD) protection have been used for some time. Generally, such ESD supply clamps protect an IC against static discharge by non-destructively passing large currents through a low impedance path of a discharge transistor for a relatively short, controlled time.
On recent low-power or battery-powered products, power supplies for internal ICs are ramped up often and quickly, with ramp times now in the 10 s of microseconds, and heading lower. ESD supply clamps have a power-up current transient that was easy to mitigate when the ramp times were at the millisecond level, as in earlier designs. For example, in the past, a pull-up resistor of a few hundred ohms has been connected to the gate of the discharge transistor for overshoot reduction of the power-up current transient and for power savings. But now the performance expectation of low power draws through the newly speeded-up power ramps creates a need for new ESD supply clamp design involving more aggressive power management.